1. Field of the Invention
The present invention relates to a memory device and a fabricating method thereof. More particularly, the present invention relates to a flash memory cell and a fabricating method thereof.
2. Description of the Related Art
Non-volatile memory is currently used inside many types of electronic devices for holding structural, program and other repeatedly accessible data. Flash memory is one type of non-volatile memory that can be repeatedly accessed. In fact, flash memory is a type of electrically erasable programmable read only memory (EEPROM) device that allows multiple data writing, reading and erasing operations. Furthermore, the stored data will be retained even after power to the device is removed. With these advantages, flash memory has been broadly applied in personal computer and electronic equipment.
FIG. 1 is a diagram showing a schematic layout of the conventional flash memory cells. FIGS. 2A through 2C are schematic cross-sectional views along line I–I′ of FIG. 1 showing the steps for fabricating a conventional memory cell. FIG. 3A is a schematic cross-sectional view along line II–II′ of FIG. 1 showing the corresponding memory cell structure in FIG. 2A. FIG. 3B is a schematic cross-sectional view along line II–II′ of FIG. 1 showing the corresponding memory cell structure in FIGS. 2B and 2C.
As shown in FIGS. 2A and 3A, a plurality of linear device isolation structures 102 is formed on a substrate 100. Using the device isolation structure 102 as a mask, a well region 104 and doped region 106 are formed in the substrate 100. Thereafter, a tunneling dielectric layer 108 is formed over the doped region 106 of the substrate 100. A patterned conductive layer 110 is formed over the tunneling dielectric layer 108. The patterned conductive layer 110 has a plurality of linear strips aligned in parallel to each other.
As shown in FIGS. 2B and 3B, an inter-gate dielectric layer 112 is formed over the substrate 100 and the patterned conductive layer 110. Thereafter, a conductive layer 114 is formed over the inter-gate dielectric layer 112. As shown in FIGS. 2C and 3B, the conductive layer 114, the inter-gate dielectric layer 112 and the patterned conductive layer 110 are patterned in the same processing step to form a plurality of linear control gates 114a and linear floating gates 110a and expose the substrate 100 on each side of the floating gates 110a. Thereafter, a doped region 116 is formed in the substrate 100 on each side of the floating gates 110a to serve as the source/drain regions of the flash memory cell. Meanwhile, the doped region 106 between the neighboring doped regions 116 serves as the channel region of the flash memory cell.
At present, semiconductor fabrication techniques have been developing towards the production devices having a higher level of integration and a smaller dimension. In the process of miniaturizing semiconductor devices, many types of technical difficulties are encountered. Using the aforementioned process of fabricating a conventional flash memory cell as an example, the overlapping area between the floating gate 110a and the control gate 114a must be increased to produce a higher coupling ratio when the dimension of each memory cell is reduced. Thus, the floating gate 110a must have a sufficient thickness and the distance separating two neighboring floating gates 110 over the device isolation structure 102 must be as small as possible. In other words, the patterned conductive layer 110 in FIG. 3A must have a definite minimum thickness and the opening 113 must have a dimension as small as possible. To meet these criteria, the aspect ratio of the openings 113 in the patterned conductive layer 110 is very high rendering the process of etching the patterned conductive layer 110 extremely difficult.
Furthermore, in the etching process for forming the control gates 114a and the control gates 110a, the etching period is frequently extended in order to remove any trace of residual inter-gate dielectric layer 112. This often causes an over-etching of the device isolation structures 102 leading to a possible increase in the leakage current from the device. Ultimately, the electrical performance of the devices is likely to deteriorate.